dc.citation.endPage |
1835 |
- |
dc.citation.number |
10 |
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dc.citation.startPage |
1833 |
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dc.citation.title |
IEEE TRANSACTIONS ON ELECTRON DEVICES |
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dc.citation.volume |
49 |
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dc.contributor.author |
Choi, YJ |
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dc.contributor.author |
Choi, BY |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.contributor.author |
Lee, JD |
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dc.contributor.author |
Park, BG |
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dc.date.accessioned |
2023-12-22T11:36:48Z |
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dc.date.available |
2023-12-22T11:36:48Z |
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dc.date.created |
2014-10-27 |
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dc.date.issued |
2002-10 |
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dc.description.abstract |
We have proposed and fabricated a novel 50-nm nMOSFET with side-gates, which induce inversion layers for virtual source/drain extensions (SDE). The 50-nm nMOSFETs show excellent suppression of the short channel effect and reasonable current drivability [subthreshold swing of 86 mV/decade, drain-induced barrier lowering (DIBL) of 112 mV, and maximum transconductance (g(m)) of 470 muS/mum at V-D = 1.5 V], resulting from the ultra-shallow virtual SDE junction. Since both the main gate and the side-gate give good cut-off characteristics, a possible advantage of this structure in the application to multi-input NAND gates was investigated. |
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dc.identifier.bibliographicCitation |
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.49, no.10, pp.1833 - 1835 |
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dc.identifier.doi |
10.1109/TED.2002.803648 |
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dc.identifier.issn |
0018-9383 |
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dc.identifier.scopusid |
2-s2.0-0036772966 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/7937 |
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dc.identifier.url |
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0036772966 |
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dc.identifier.wosid |
000178420500024 |
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dc.language |
영어 |
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dc.publisher |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
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dc.title |
A new 50-nm nMOSFET with side-gates for virtual source-drain extensions |
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dc.type |
Article |
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dc.description.journalRegisteredClass |
scopus |
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