A SPICE model of realistic single-electron transistors and its application to multiple-valued logic

Abstract

A SPICE (simulation program with integrated circuit emphasis) model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs and was implemented into a conventional circuit simulator. In the proposed model, the SET current calculated using an analytic model is combined with the parasitic MOSFET (metal-oxide semiconductor field effect transistor) characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. An extensive comparison leads to good agreement with a reasonable level of accuracy, whre divergent physical phenomena, such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias, are considered. Employing the SET SPICE model, we confirmed the feasibility of CMOS (complementary metaloxide semiconductor)/SET hybrid multiple-valued logics (MVLs). A periodic binary converter with a proposed complementary self-biasing scheme showed improved characteristics in terms of stability and performance.