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Lee, Jongeun
Intelligent Computing and Codesign Lab.
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dc.citation.endPage 236 -
dc.citation.number 4 -
dc.citation.startPage 229 -
dc.citation.title JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE -
dc.citation.volume 5 -
dc.contributor.author Lee, Jongeun -
dc.contributor.author Kwon, Woo-Cheol -
dc.contributor.author Kim, Tae-Hun -
dc.contributor.author Chung, Eui-Young -
dc.contributor.author Cho, Kyu-Myung -
dc.contributor.author Kong, Jeong-Taek -
dc.contributor.author Eo, Soo-Kwan -
dc.contributor.author Gwilt, David -
dc.date.accessioned 2023-12-22T10:10:42Z -
dc.date.available 2023-12-22T10:10:42Z -
dc.date.created 2014-10-28 -
dc.date.issued 2005-12 -
dc.description.abstract This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time. -
dc.identifier.bibliographicCitation JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.5, no.4, pp.229 - 236 -
dc.identifier.issn 1598-1657 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/7856 -
dc.language 영어 -
dc.publisher IEEK PUBLICATION CENTER -
dc.title System Level Architecture Evaluation and Optimization:an Industrial Case Study with AMBA3 AXI -
dc.type Article -

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