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Yoon, Heein
Advanced Circuits and Electronics Lab.
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dc.citation.conferencePlace US -
dc.citation.endPage 332 -
dc.citation.startPage 330 -
dc.citation.title IEEE International Solid-State Circuits Conference -
dc.contributor.author Yoo, S. -
dc.contributor.author Park, S. -
dc.contributor.author Choi, S. -
dc.contributor.author Cho, Y. -
dc.contributor.author Yoon, Heein -
dc.contributor.author Hwang, C. -
dc.contributor.author Choi, J. -
dc.date.accessioned 2024-01-31T22:07:54Z -
dc.date.available 2024-01-31T22:07:54Z -
dc.date.created 2022-03-10 -
dc.date.issued 2021-02-13 -
dc.description.abstract As the utilization of the mm-wave spectrum becomes active, designers' interests are shifting to even higher frequencies in the W-band. Given their potential use as carrier frequencies for the next-generation mobiles (i.e., beyond 5G), these W-band signals must have ultra-low phase noise (PN). Currently, the most popular solution to generate such frequencies is with a cascaded architecture: a first-stage PLL generates a low-PN signal at a relatively low frequency at which the VCO LC tank has a high Q factor, and following frequency multipliers (FMs) increase the frequency to the W-band [1]. Although various FMs have been proposed, all of them are limited in their ability to achieve a high multiplication factor, M. Push-push or harmonic-selection circuits have high conversion losses. Injection-locked FMs (ILFMs) require multiple stages due to their narrow lock ranges, which increase power consumption and complexity. Thus, single-stage direct PLLs [2-4] would be preferred if they could have a sufficiently wide loop bandwidth to suppress the poor PN of a W-band VCO. Subsampling PLLs (SSPLLs) are suitable for extending the bandwidth since they have low in-band PN due to the high phase-error (φ ERR ) detection gain of a subsampling phase detector (PD). Nevertheless, when SSPLLs operate in the W-band, the degradation of PN is unavoidable because the φ ERR detection gain decreases as the frequency of the VCO, f VCO , increases. As described at the left of Fig. 23.4.1, when the switch of the PD, SWPD, is closed, the output of the PD, SPD, should track the signal of the VCO, S VCO , closely. However, when f VCO increases to the W-band, the amplitude of SPD is reduced significantly by a parasitic pole that is present due to the turned-on resistance of SW PD , R ON , and the sampling capacitor, CS. When SWPD is turned off, φ ERR is detected in SPD, but its magnitude is already suppressed significantly relative to that in SVCO. This effect also can be interpreted in the frequency domain where S VCO is suppressed by a low-pass filter before the information of φ ERR is extracted at the baseband frequencies. -
dc.identifier.bibliographicCitation IEEE International Solid-State Circuits Conference, pp.330 - 332 -
dc.identifier.doi 10.1109/ISSCC42613.2021.9365956 -
dc.identifier.issn 0193-6530 -
dc.identifier.scopusid 2-s2.0-85102360217 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/77622 -
dc.language 영어 -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS -
dc.type Conference Paper -
dc.date.conferenceDate 2021-02-13 -

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