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An Optimal Gate Design for the Synthesis of Ternary Logic Circuits
- Author(s)
- Kim, Sunmean
- Advisor
- Kang, Seokhyeong
- Issued Date
- 2018-02
- URI
- https://scholarworks.unist.ac.kr/handle/201301/72269 http://unist.dcollection.net/common/orgView/200000009605
- Publisher
- Ulsan National Institute of Science and Technology
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