NONLINEARITY COMPENSATION AND HIGH VOLTAGE PROTECTION OF CURRENT STEERING DAC

Abstract

Current steering digital to analog converter (DAC) always suffer from lots of problem like mismatch errors and timing related dynamic errors. Diverse studies from art-of-the-state suggest methods for compensate some of these errors. Typical examples of compensation methods are segmentation, quad-quadrant (Q2) random walk and dynamic element matching (DEM). These compensation methods reduce lots of fundamental errors while used together with other proposed technique in this thesis. This thesis propose two structure. One structure is related with industrial applications. Industrial application usually requires 10V swing for voltage driving and 20mA swing for current driving. Conventional industrial DAC satisfy these swing requirement with high voltage driving amplifier. But driving amplifier consumes additional power and adds its own distortion to output signal. High voltage protection structure is proposed to satisfy industrial swing requirement and solve the problems of driving amplifier combined DAC. Proposed high voltage protection structure decrease cost of manufacturing by decreasing number of high voltage transistor. Proposed structure also increases linearity by changing effective output impedance and decreases additional current consumption while satisfying industrial swing requirement. The other proposed structure is related with resolution improving. Recent current steering DAC becomes fast enough to cover over GHz range with developing technologies. However resolution is still limited by matching properties. Current steering DAC with resolution improving sigma-delta (∑Δ) modulation is proposed. It increase resolution by noise shaping of ∑Δ modulation while sacrificing speed. It still fast because recent current steering DAC is very fast. ∑Δ modulator only randomize LSB side and shaping LSB related noise. Q2 random walk and DEM are also included to randomize MSB side and reduce MSB related noise. Two version of test chips are tested. 12bit random rotation-based binary-weighted (RRSB) DEM current steering DAC is implemented in 130nm compliment metal-oxide semiconductor (CMOS) process. Test result shows the effect of MSB side randomizing DEM from art-of-the-state. Proposed 14bit resolution improved DAC with high voltage protection is implemented in 180nm bipolar + compliment + double-diffused metal oxide semiconductor (BCDMOS) process. Test result verify performance improvement in frequency domain. Operation voltage and resolution of DAC can be changed by each proposed method. DAC can be applied to various application that require various operation voltage and resolution by using both method properly.