There are no files associated with this item.
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 390 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 383 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 60 | - |
dc.contributor.author | Lee, Kyeong-Jae | - |
dc.contributor.author | Park, Hyesung | - |
dc.contributor.author | Kong, Jing | - |
dc.contributor.author | Chandrakasan, Anantha P. | - |
dc.date.accessioned | 2023-12-22T04:15:41Z | - |
dc.date.available | 2023-12-22T04:15:41Z | - |
dc.date.created | 2014-10-07 | - |
dc.date.issued | 2013-01 | - |
dc.description.abstract | We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18-μm CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11× faster speeds and 1.54× lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.60, no.1, pp.383 - 390 | - |
dc.identifier.doi | 10.1109/TED.2012.2225150 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.scopusid | 2-s2.0-84871800961 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/6971 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6353910/ | - |
dc.identifier.wosid | 000316816200057 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | CMOS integrated circuits | - |
dc.subject.keywordAuthor | graphene | - |
dc.subject.keywordAuthor | interconnects | - |
dc.subject.keywordPlus | 65 NM CMOS | - |
dc.subject.keywordPlus | LEVEL CONVERTER | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordPlus | CONDUCTIVITY | - |
dc.subject.keywordPlus | OPERATION | - |
dc.subject.keywordPlus | PROCESSOR | - |
dc.subject.keywordPlus | CIRCUITS | - |
dc.subject.keywordPlus | ROBUST | - |
dc.subject.keywordPlus | FILMS | - |
dc.subject.keywordPlus | MV | - |
Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Tel : 052-217-1404 / Email : scholarworks@unist.ac.kr
Copyright (c) 2023 by UNIST LIBRARY. All rights reserved.
ScholarWorks@UNIST was established as an OAK Project for the National Library of Korea.