High efficient HEVC (H.265) codec design for mobile applications

Abstract

In this work, we implemented HEVC (H.265) codec and evaluate its performance. HEVC is claimed to be able to reduce the bit rate by 50% compared to H.264 AVC, at the same video quality. The trade-off is that HEVC codec is much more complex than H.264 AVC in terms of computation overload. Because a lot of multiplication operations are inevitable in these algorithms. In hardware implementation, if we use too many multipliers, the total number of logic elements (gates) will be very large. This huge amount of logic elements will increase the total area of integrated circuits (IC) chip, as well as the total power consumption. Instead, in traditional application processor based system, one multiplier is reused and the instructions are pipelined to improve the processing throughput. In modern SOC system, GPU is also introduce to accelerate the video/image processing speed. In this paper, we will evaluate the performance of the HEVC implementation in a hardware/software combined implementation of HEVC, which can take advantages of both hardware and software designs.