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DC Field | Value | Language |
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dc.citation.endPage | 2855 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 2841 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 57 | - |
dc.contributor.author | Hwang, Chanwoong | - |
dc.contributor.author | Park, Hangi | - |
dc.contributor.author | Lee, Yongsun | - |
dc.contributor.author | Seong, Taeho | - |
dc.contributor.author | Choi, Jaehyouk | - |
dc.date.accessioned | 2023-12-21T13:43:17Z | - |
dc.date.available | 2023-12-21T13:43:17Z | - |
dc.date.created | 2022-02-11 | - |
dc.date.issued | 2022-09 | - |
dc.description.abstract | This work presents a low-jitter and low-spur, fractional-N ring-oscillator-based digital phase-locked loop (RO-DPLL). First, to suppress fractional spurs, the probability-density-shaping delta-sigma modulator (PDS-Delta sigma M) is presented. Since the output codes of the PDS-Delta sigma M are designed to have a time-invariant probability density function (PDF), they have spur immunity to any nonlinearity (NL) of the digital-to-time converter (DTC). In addition, by using a special dither consisting of uniform random numbers (URNs) based on the dithered quantization theorems, the PDS-Delta sigma M can also suppress fractional spurs due to the NL of other loop-building circuits. Second, the DTC's second-/third-order nonlinearity cancellation (DST-NLC) technique is presented to reduce the quantization noise (Q-noise), thereby reducing the rms jitter. The proposed RO-DPLL was fabricated in 65-nm CMOS, and it used a 0.146-mm(2) silicon area and 9.27-mW power. At a near-integer-N frequency, i.e., near 5.3 GHz, the measured rms jitter and the fractional spur were less than 365 fs and -63 dBc, respectively. | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2841 - 2855 | - |
dc.identifier.doi | 10.1109/JSSC.2022.3141782 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.scopusid | 2-s2.0-85123701821 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/59231 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9690576 | - |
dc.identifier.wosid | 000748529700001 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article; Early Access | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Codes | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | Probability density function | - |
dc.subject.keywordAuthor | Phase locked loops | - |
dc.subject.keywordAuthor | Bandwidth | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | Silicon | - |
dc.subject.keywordAuthor | Digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | digital-to-time converter (DTC) | - |
dc.subject.keywordAuthor | fractional spur | - |
dc.subject.keywordAuthor | nonlinearity (NL) | - |
dc.subject.keywordAuthor | ring digitally controlled oscillator (RDCO) | - |
dc.subject.keywordAuthor | rms jitter | - |
dc.subject.keywordPlus | SUBSAMPLING PLL | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | 5G | - |
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