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DC Field | Value | Language |
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dc.citation.endPage | 3151 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 3138 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 67 | - |
dc.contributor.author | Kim, Sunmean | - |
dc.contributor.author | Lee, Sung-Yun | - |
dc.contributor.author | Park, Sunghye | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.contributor.author | Kang, Seokhyeong | - |
dc.date.accessioned | 2023-12-21T17:07:32Z | - |
dc.date.available | 2023-12-21T17:07:32Z | - |
dc.date.created | 2020-09-14 | - |
dc.date.issued | 2020-09 | - |
dc.description.abstract | We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.9, pp.3138 - 3151 | - |
dc.identifier.doi | 10.1109/TCSI.2020.2990748 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.scopusid | 2-s2.0-85090402259 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/48197 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9089220 | - |
dc.identifier.wosid | 000564305500022 | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering | - |
dc.relation.journalResearchArea | Engineering, Electrical & Electronic | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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