dc.citation.conferencePlace |
GR |
- |
dc.citation.conferencePlace |
Kos, GREECE |
- |
dc.citation.endPage |
2120 |
- |
dc.citation.startPage |
2117 |
- |
dc.citation.title |
IEEE International Symposium on Circuits and Systems |
- |
dc.contributor.author |
Bien, Franklin |
- |
dc.contributor.author |
Hur, Youngsik |
- |
dc.contributor.author |
Maeng, Moonkyun |
- |
dc.contributor.author |
Kim, Hyoungsoo |
- |
dc.contributor.author |
Gebara, Edward |
- |
dc.contributor.author |
Laskar, Joy |
- |
dc.date.accessioned |
2023-12-20T05:09:00Z |
- |
dc.date.available |
2023-12-20T05:09:00Z |
- |
dc.date.created |
2014-12-23 |
- |
dc.date.issued |
2006-05-21 |
- |
dc.description.abstract |
In order to realize adjustable equalization over various backplane channel configurations, a reconfigurable fully-integrated equalizer IC is presented. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-Forward Equalizer (FFE) topology with Finite Impulse Response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, wide-range tunable active delay line, variable tap-gain multiplier and 8-bit digital-to-analog converter (DAC) were fabricated in a 0.18-μm standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations. |
- |
dc.identifier.bibliographicCitation |
IEEE International Symposium on Circuits and Systems, pp.2117 - 2120 |
- |
dc.identifier.isbn |
978-078039390-5 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46936 |
- |
dc.language |
영어 |
- |
dc.publisher |
IEEE CAS Society |
- |
dc.title |
A reconfigurable fully-integrated 0. 18-mu m CMOS feed-forward equalizer IC for 10-Gb/sec backplane links |
- |
dc.type |
Conference Paper |
- |
dc.date.conferenceDate |
2006-05-21 |
- |