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DC Field | Value | Language |
---|---|---|
dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | San Francisco, CA | - |
dc.citation.endPage | 121 | - |
dc.citation.startPage | 119 | - |
dc.citation.title | 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.contributor.author | Song, Ki-Whan | - |
dc.contributor.author | Baek, Gwanghyeon | - |
dc.contributor.author | Lee, Sang-Hoon | - |
dc.contributor.author | Kim, Dae Hwan | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.contributor.author | Woo, Dong-Soo | - |
dc.contributor.author | Sim, Jae Sung | - |
dc.contributor.author | Lee, Jong Duk | - |
dc.date.accessioned | 2023-12-20T06:06:36Z | - |
dc.date.available | 2023-12-20T06:06:36Z | - |
dc.date.created | 2014-12-23 | - |
dc.date.issued | 2003-08-12 | - |
dc.description.abstract | A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of CMOS/SET hybrid logic. It is demonstrated that a universal literal gate with complementary self-biasing scheme operates quite well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation degrades severely. | - |
dc.identifier.bibliographicCitation | 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003, pp.119 - 121 | - |
dc.identifier.doi | 10.1109/NANO.2003.1231729 | - |
dc.identifier.issn | 1944-9399 | - |
dc.identifier.scopusid | 2-s2.0-11244305802 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/46891 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/1231729 | - |
dc.language | 영어 | - |
dc.publisher | 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 | - |
dc.title | Realistic Single-Electron Transistor Modeling and Novel CMOS/SET Hybrid Circuits | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2003-08-12 | - |
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