dc.citation.conferencePlace |
KO |
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dc.citation.endPage |
244 |
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dc.citation.startPage |
243 |
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dc.citation.title |
13th International SoC Design Conference (ISOCC 2016) |
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dc.contributor.author |
Kim, Young Bae |
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dc.contributor.author |
Tong, Qiang |
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dc.contributor.author |
Choi, Ken |
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dc.contributor.author |
Lee, Yun-Sik |
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dc.date.accessioned |
2023-12-19T20:06:17Z |
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dc.date.available |
2023-12-19T20:06:17Z |
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dc.date.created |
2017-02-10 |
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dc.date.issued |
2016-10-23 |
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dc.description.abstract |
In deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to build the cache in Systemon- Chip (SOC). In this paper, a low power 8-T SRAM cell, based on carbon nanotube field effect transistor (CNFET), is proposed to circumvent the leakage power issue. Experiment datas show that the proposed SRAM cell can save 97.94% static power consumption compared to existing 6T CNFET SRAM cell. In case of writing, the proposed SRAM cell comsumes 39.27% less power than the traditional SRAM cell for writing 0 and 58.79% less for writing 1. Also, because of the adoption of a colaborated voltage sense amplifier and independent read component, our 8T SRAM shows much improved dealy performance, the delay is observed to reduce by approximate 30% in write operation and approximate 90% in read operation. |
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dc.identifier.bibliographicCitation |
13th International SoC Design Conference (ISOCC 2016), pp.243 - 244 |
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dc.identifier.doi |
10.1109/ISOCC.2016.7799768 |
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dc.identifier.scopusid |
2-s2.0-85010282131 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46634 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/7799768/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
Novel 8-T CNFET SRAM Cell Design for the Future Ultra-low Power Microelectronics |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2016-10-23 |
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