Configurable range memory for effective data reuse on programmable accelerators
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- Configurable range memory for effective data reuse on programmable accelerators
- Lee, Jongeun; Seo, Seongseok; Paek, Jongkyung; Choi, Kiyoung
- Array mapping; Coarse-grained reconfigurable architecture; Compilercontrolled memories; On-chip memory architectures and management; Scratchpads
- Issue Date
- ASSOC COMPUTING MACHINERY
- ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.19, no.2, pp.1 - 22
- While programmable accelerators such as application-specific processors and reconfigurable architectures can dramatically speed up compute-intensive kernels of an application, application performance can still be severely limited by the communication between processors. To minimize the communication overhead, a shared memory such as a scratchpad memory may be employed between the main processor and the accelerator coprocessor. However, this setup poses a significant challenge to the main processor, which now must manage data on the scratchpad explicitly, resulting in superfluous data copying due to the inflexibility of a scratchpad. In this article, we present an enhancement of a scratchpad, Configurable Range Memory (CRM), whose address range can be reprogrammed to minimize unnecessary data copying between processors and therefore promote data reuse on the accelerator, and also present a software management algorithm for the CRM. Our experimental results involving detailed simulation of full multimedia applications demonstrate that our CRM architecture can reduce the communication overhead quite effectively, reducing the kernel execution time by up to 28% and the application runtime by up to 12.8%, in addition to considerable system energy reduction, compared to the conventional architecture based on a scratchpad.
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