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Kim, Kyung Rok
Nano-Electronic Emerging Devices Lab.
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dc.citation.endPage 22 -
dc.citation.number 10 -
dc.citation.startPage 14 -
dc.citation.title 전자공학회논문지 -
dc.citation.volume 47 -
dc.contributor.author Cho, Seongjae -
dc.contributor.author Kim, Kyung Rok -
dc.contributor.author Park, Byung-Gook -
dc.contributor.author Kang, In Man -
dc.date.accessioned 2023-12-22T06:42:53Z -
dc.date.available 2023-12-22T06:42:53Z -
dc.date.created 2013-07-11 -
dc.date.issued 2010-10 -
dc.description.abstract 기존의 n-type metal-oxide-semiconductor field effect transistor(NMOSFET)은 n+/p(+)/n+ type의 이온 주입을 통하여 소스/채널/드레인 영역을 형성하게 된다. 30 nm 이하의 채널 길이를 갖는 초미세 소자를 제작함에 있어서 설계한 유효 채널 길이를 정확하게 얻기 위해서는 주입된 이온들을 완전히 activation하여 전류 수준을 향상시키면서도 diffusion을 최소화하기 위해 낮은 thermal budget을 갖도록 공정을 설계해야 한다. 실제 공정에서의 process margin을 완화할 수 있도록 오히려 p-type 채널을 형성하지 않으면서도 기존의 NMOSFET의 동작을 온전히 구현할 수 있는 junctionless(JL) MOSFET이 연구중이다. 본 논문에서는 3차원 소자 시뮬레이션을 통하여 silicon nanowire(SNW) 구조에 접목시킨 JL MOSFET을 최적 설계하고 그러한 조건의 소자에 대하여 conductance, maximum oscillation frequency(fmax), current gain cut-off frequency(fT) 등의 기본적인 고주파 특성을 분석한다. 채널 길이는 30 nm이며 설계 변수는 채널 도핑 농도와 채널 SNW의 반지름이다. 최적 설계된 JL SNWNMOSFET에 대하여 동작 조건(VGS = VDS = 1.0 V)에서 각각 367.5 GHz, 602.5 GHz의 fT, fmax를 얻을 수 있었다.

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).
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dc.identifier.bibliographicCitation 전자공학회논문지, v.47, no.10, pp.14 - 22 -
dc.identifier.issn 1016-135X -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/4294 -
dc.identifier.url http://www.dbpia.co.kr/Article/1374653 -
dc.language 한국어 -
dc.publisher 대한전자공학회 -
dc.title.alternative Optimum Design of Junctionless MOSFET Based on Silicon Nanowire Structure and Analysis on Basic RF Characteristics -
dc.title 실리콘 나노 와이어 기반의 무접합 MOSFET의 최적 설계 및 기본적인 고주파 특성 분석 -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.identifier.kciid ART001490728 -
dc.description.journalRegisteredClass kci -

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