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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Architecture Customization of On-Chip Reconfigurable Accelerators

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Title
Architecture Customization of On-Chip Reconfigurable Accelerators
Author
Yoon, Jonghee W.Lee, JongeunPark, SanghyunKim, YongjooLee, JinyongPaek, YunheungCho, Doosan
Keywords
Coarse-grained reconfigurable arrays; Customization; Graph edit; Inexact matching; Interconnect architectures
Issue Date
201310
Publisher
ASSOC COMPUTING MACHINERY
Citation
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.18, no.4, pp.1 - 22
Abstract
Integrating coarse-grained reconfigurable architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without performing explicit design space exploration. In this article we present a novel methodology for incremental interconnect customization of CGRAs that can suggest a new interconnection architecture which is able to maximize the performance for a given set of application kernels while minimizing the hardware cost. In our methodology, we translate the problem of interconnect customization into that of inexact graph matching, and we devised a heuristic for A search algorithm to efficiently solve the inexact graph matching problem. Our experimental results demonstrate that our customization method can quickly find application-optimized interconnections that exhibit 80% higher performance on average compared to the base architecture which has mesh interconnections, with little energy and hardware increase in interconnections and muxes.
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DOI
http://dx.doi.org/10.1145/2493384
ISSN
1084-4309
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ECE_Journal Papers

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