LCD-TV System with 2.8Gbps/Lane Intra-Panel Interface for 3D TV Applications

Abstract

This paper presents LCD-TV system with newly proposed 2.8Gbps/lane intra-panel interface for 3D TV applications. The proposed intra-panel interface transfers data in a point-to-point manner with embedded clock. Scrambling scheme was applied to stabilize loop bandwidth of bang-bang CDR, and to minimize EMI radiation. Timing controller (TCON) and source driver (SD) are implemented using 65nm/1.2V and 0.18um/1.8V CMOS processes, respectively. 2.8Gbps operation was verified by increasing horizontal blanking period while driving a 55-inch Full-HD LCD panel with 8-bit RGB and 120Hz frame rate. The proposed interface demonstrates the possibility of implementing an intrapanel system of 240Hz FHD LCD-TV for 3D displays with just one pair of differential data lines per SD.