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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Improving Performance of Nested Loops on Reconfigurable Array Processors

Cited 0 times inthomson ciCited 7 times inthomson ci
Title
Improving Performance of Nested Loops on Reconfigurable Array Processors
Author
Kim, YongjooLee, JongeunMai, Toan X.Paek, Yunheung
Keywords
Co-processors; Coarse grained reconfigurable architecture; Communication delays; Compilation; Conventional approach; Cooperative schemes; Execution time; Improving performance; Loop nests; Nested Loops; Outer loop; Reconfigurable array; Set-up time; Software pipelining; Steady state performance; Two processors
Issue Date
201201
Publisher
ASSOC COMPUTING MACHINERY
Citation
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, v.8, no.4, pp.1 - 23
Abstract
Pipelining algorithms are typically concerned with improving only the steady-state performance, or the kernel time. The pipeline setup time happens only once and therefore can be negligible compared to the kernel time. However, for Coarse-Grained Reconfigurable Architectures (CGRAs) used as a coprocessor to a main processor, pipeline setup can take much longer due to the communication delay between the two processors, and can become significant if it is repeated in an outer loop of a loop nest. In this paper we evaluate the overhead of such non-kernel execution times when mapping nested loops for CGRAs, and propose a novel architecture-compiler cooperative scheme to reduce the overhead, while also minimizing the number of extra configurations required. Our experimental results using loops from multimedia and scientific domains demonstrate that our proposed techniques can greatly increase the performance of nested loops by up to 2.87 times compared to the conventional approach of accelerating only the innermost loops. Moreover, the mappings generated by our techniques require only a modest number of configurations that can fit in recent reconfigurable architectures.
URI
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DOI
http://dx.doi.org/10.1145/2086696.2086711
ISSN
1544-3566
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