dc.citation.conferencePlace |
JA |
- |
dc.citation.conferencePlace |
Yokohama |
- |
dc.citation.title |
IEEE Symposium on Low-Power and High-Speed Chips |
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dc.contributor.author |
Park, Junyoung |
- |
dc.contributor.author |
Hong, Injoon |
- |
dc.contributor.author |
Kim, Gyeonghoon |
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dc.contributor.author |
Kim, Youchang |
- |
dc.contributor.author |
Lee, Kyuho |
- |
dc.contributor.author |
Park, Seongwook |
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dc.contributor.author |
Bong, Kyeongryeol |
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dc.contributor.author |
Yoo, Hoi-Jun |
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dc.date.accessioned |
2023-12-20T01:07:32Z |
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dc.date.available |
2023-12-20T01:07:32Z |
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dc.date.created |
2018-08-07 |
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dc.date.issued |
2013-04-17 |
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dc.description.abstract |
Multiple granularity parallel core architecture is proposed to accelerate object recognition with low area and energy consumption. By adopting task-level optimized cores with different parallelism and complexity, the proposed processor achieves real-time object recognition with 271.4 GOPS peak performance. In addition, content-aware fine-grained task scheduling is proposed to enable low power real-time object recognition on 30fps 720p HD video streams. As a result, the object recognition processor achieves 9.4nJ/pixel energy efficiency and 25.8 GOPS/W·mm 2 power-area efficiency in O.13um CMOS technology. |
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dc.identifier.bibliographicCitation |
IEEE Symposium on Low-Power and High-Speed Chips |
- |
dc.identifier.doi |
10.1109/CoolChips.2013.6547917 |
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dc.identifier.scopusid |
2-s2.0-84881342755 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/37402 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/6547917/ |
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dc.language |
영어 |
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dc.publisher |
16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013 |
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dc.title |
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2013-04-17 |
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