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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

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Title
A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files
Author
Lee, JongeunShrivastava, A.
Keywords
Compiler-architecture hybrid; embedded processor design; energy; partially protected register file (PPRF); register file vulnerability (RFV); reliability
Issue Date
201007
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.29, no.7, pp.1018 - 1027
Abstract
For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.
URI
http://scholarworks.unist.ac.kr/handle/201301/3740
DOI
http://dx.doi.org/10.1109/TCAD.2010.2049050
ISSN
0278-0070
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ECE_Journal Papers

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