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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Binary acceleration using coarse-grained reconfigurable architecture

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Title
Binary acceleration using coarse-grained reconfigurable architecture
Author
Paek, Jong KyungChoi, KiyoungLee, Jongeun
Keywords
Embedded and cyber-physical systems; Real-time systems
Issue Date
201009
Publisher
ACM
Citation
ACM SIGARCH Computer Architecture News, v.38, no.4, pp.33 - 39
Abstract
Coarse-grained reconfigurable architectures (CGRAs) have been well-researched and shown to be particularly effective in acceleration of data-intensive applications. However, practical difficulties in application mapping have hindered their widespread adoption. Typically, an application must be modified manually or by using special compilers and design tools in order to fully exploit the architecture. This incurs considerable design costs to the application developer and reduces software portability. In this paper, we propose a framework for automatic transformation of an application at binary-level, with which the user can execute an arbitrary application on the CGRA. Our approach analyzes the binary code and determines which portions of the program to accelerate, maps them to the reconfigurable array, then modifies the binary code appropriately to run on the CGRA. We describe the overall process of our framework, and present solutions to several problems that arise from such an approach. Results from our preliminary experiments show that we are able to achieve speedup of up to 14.8.
URI
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DOI
http://dx.doi.org/10.1145/1926367.1926374
ISSN
0163-5964
Appears in Collections:
ECE_Journal Papers

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