dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
Hilton Hawaiian VillageHonolulu |
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dc.citation.endPage |
171 |
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dc.citation.startPage |
170 |
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dc.citation.title |
2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016) |
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dc.contributor.author |
Shin, Sunhae |
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dc.contributor.author |
Jang, Esan |
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dc.contributor.author |
Jeong, Jae Won |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.date.accessioned |
2023-12-19T20:37:41Z |
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dc.date.available |
2023-12-19T20:37:41Z |
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dc.date.created |
2016-11-28 |
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dc.date.issued |
2016-06-12 |
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dc.description.abstract |
We demonstrate a standard ternary inverter (STI) by using gate-last CMOS process with novel I-V characteristics based on off-state mechanism. Though the controllable α′ and β′ with respective design parameters, STI operation at VDD= 1 V have been investigated with static noise margin (SNM) of 210 mV. |
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dc.identifier.bibliographicCitation |
2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016), pp.170 - 171 |
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dc.identifier.doi |
10.1109/SNW.2016.7578036 |
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dc.identifier.isbn |
978-150900726-4 |
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dc.identifier.scopusid |
2-s2.0-84994701151 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/37342 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/7578036/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
Demonstration of standrad ternary inverter based on CMOS technology |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2016-06-12 |
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