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Kim, Kyung Rok
Nano-Electronic Emerging Devices Lab.
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dc.citation.conferencePlace US -
dc.citation.conferencePlace Hilton Hawaiian VillageHonolulu -
dc.citation.endPage 171 -
dc.citation.startPage 170 -
dc.citation.title 2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016) -
dc.contributor.author Shin, Sunhae -
dc.contributor.author Jang, Esan -
dc.contributor.author Jeong, Jae Won -
dc.contributor.author Kim, Kyung Rok -
dc.date.accessioned 2023-12-19T20:37:41Z -
dc.date.available 2023-12-19T20:37:41Z -
dc.date.created 2016-11-28 -
dc.date.issued 2016-06-12 -
dc.description.abstract We demonstrate a standard ternary inverter (STI) by using gate-last CMOS process with novel I-V characteristics based on off-state mechanism. Though the controllable α′ and β′ with respective design parameters, STI operation at VDD= 1 V have been investigated with static noise margin (SNM) of 210 mV. -
dc.identifier.bibliographicCitation 2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016), pp.170 - 171 -
dc.identifier.doi 10.1109/SNW.2016.7578036 -
dc.identifier.isbn 978-150900726-4 -
dc.identifier.scopusid 2-s2.0-84994701151 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/37342 -
dc.identifier.url http://ieeexplore.ieee.org/document/7578036/ -
dc.language 영어 -
dc.publisher IEEE -
dc.title Demonstration of standrad ternary inverter based on CMOS technology -
dc.type Conference Paper -
dc.date.conferenceDate 2016-06-12 -

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