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Author

Choi, Jaehyouk
Integrated Circuits and Systems Lab (ICSL)
Research Interests
  • RF/Analog/Mixed IC design, low power CMOS IC, wired/wireless TRX IC, clock generation IC

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High-resolution offset-frequency PLL using properties of co-prime numbers

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Title
High-resolution offset-frequency PLL using properties of co-prime numbers
Author
Choi, JaehyoukKim, W.Park, J.Bien, Franklin
Keywords
Delay-locked loops; Frequency resolutions; High frequency resolution; Mathematical relation; Offset frequencies; Phase Locked Loop (PLL); Programmable frequency multipliers; Single-sideband mixers
Issue Date
201211
Publisher
INST ENGINEERING TECHNOLOGY-IET
Citation
ELECTRONICS LETTERS, v.48, no.24, pp.1522 - 1523
Abstract
A new offset-frequency phase-locked loop (PLL) that realises high-frequency resolution based on a mathematical relation between the output frequency and the offset frequency is proposed. The proposed PLL achieved a 0.1 MHz frequency resolution while using a 1.1 MHz reference clock. The PLL consisted of a main PLL, a delay-locked loop based programmable frequency multiplier, and a single-sideband mixer. The prototype PLL was fabricated with a 0.18 mu m CMOS technology, and occupies a 0.29 mm(2) active silicon area.
URI
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DOI
http://dx.doi.org/10.1049/el.2012.1968
ISSN
0013-5194
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ECE_Journal Papers

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