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- Bien, Franklin
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | US | - |
| dc.citation.conferencePlace | Washington | - |
| dc.citation.endPage | 445 | - |
| dc.citation.startPage | 442 | - |
| dc.citation.title | International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) | - |
| dc.contributor.author | Ryu, Myunghwan | - |
| dc.contributor.author | Bien, Franklin | - |
| dc.contributor.author | Kim, Youngmin | - |
| dc.date.accessioned | 2023-12-19T22:06:37Z | - |
| dc.date.available | 2023-12-19T22:06:37Z | - |
| dc.date.created | 2017-01-23 | - |
| dc.date.issued | 2015-09-09 | - |
| dc.description.abstract | In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed. | - |
| dc.identifier.bibliographicCitation | International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.442 - 445 | - |
| dc.identifier.doi | 10.1109/SISPAD.2015.7292356 | - |
| dc.identifier.scopusid | 2-s2.0-84959339941 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/35484 | - |
| dc.identifier.url | http://ieeexplore.ieee.org/document/7292356/ | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | Sandwiched-Gate Inverter: Novel Device Structure for Future Logic Gates | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2015-09-09 | - |
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