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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Static Analysis of Register File Vulnerability

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Title
Static Analysis of Register File Vulnerability
Author
Lee, JongeunShrivastava, Aviral
Keywords
Analysis approach; Architectural vulnerability factor; Compiler optimizations; compilers; Cost-effective protection; Inherent complexity; partially protected register file; Register files; Runtime overheads; soft error; Static estimation; Technology scaling
Issue Date
201104
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.4, pp.607 - 616
Abstract
With continuous technology scaling, soft errors are becoming an increasingly important design concern even for earth-bound applications. While compiler approaches have the potential to mitigate the effect of soft errors with minimal runtime overheads, static vulnerability estimation-an essential part of compiler approaches-is lacking due to its inherent complexity. This paper presents a static analysis approach for register file (RF) vulnerability estimation. We decompose the vulnerability of a register into intrinsic and conditional basic-block vulnerabilities. This decomposition allows us to develop a fast, yet reasonably accurate RF vulnerability estimation mechanism. We validate and compare a linear equation based method and an iterative method. Also we demonstrate a practical application of RF vulnerability estimation to compiler optimizations. Our experimental results on benchmarks from MiBench suite indicate that not only our static RF vulnerability estimation is fast and accurate, but also compiler optimizations enabled by our static estimation can achieve very cost-effective protection of register files against soft errors.
URI
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DOI
http://dx.doi.org/10.1109/TCAD.2010.2095630
ISSN
0278-0070
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ECE_Journal Papers

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