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Author

Lee, Jongeun
Renew: Reconfigurable and Neuromorphic Computing Lab
Research Interests
  • Reconfigurable processor architecture, neuromorphic processor, stochastic computing

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Return Data Interleaving for Multi-Channel Embedded CMPs Systems

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Title
Return Data Interleaving for Multi-Channel Embedded CMPs Systems
Author
Hong, FeiShrivastava, AviralLee, Jongeun
Keywords
Chip multi cores; Execution time; Memory bandwidths; Memory controller; Memory subsystems; Multi-channel; return data interleaving (RDI); Round Robin; Scheduling policies; Volume memory
Issue Date
201207
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.7, pp.1351 - 1354
Abstract
Using multi-channel memory subsystems is an efficient way of satisfying high volume memory requests from CMPs. At the same time, the imbalance between memory bandwidth and bus performance opens up new possibility of optimization before they are sent to bus. This paper presents a new memory controller design for embedded CMPs systems when the return data from the return buffer is sent back to bus. Our scheduling policy, called return data interleaving (RDI) interleaves the return data of each request in a round robin manner. Further, for each request, it sends the critical word first. To evaluate our technique, we model an Intel XScale-based CMPs using M5 simulator for CMPs simulation and DRAMsim for memory subsystem simulation and examine the performance of MiBench and SPEC2000 benchmarks. Simulation results show that for memory-bound benchmarks running on the CMPs systems with the number of cores from 6 to 16, RDI can improve the execution time by average 11% and up to 16.9%.
URI
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DOI
http://dx.doi.org/10.1109/TVLSI.2011.2157368
ISSN
1063-8210
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