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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | US | - |
| dc.citation.conferencePlace | Hilton Hawaiian VillageHonolulu | - |
| dc.citation.title | IEEE Symposium on VLSI Circuits | - |
| dc.contributor.author | Choi, Seojin | - |
| dc.contributor.author | Yoo, Seyeon | - |
| dc.contributor.author | Lee, Yongsun | - |
| dc.contributor.author | Jo, Yongwoo | - |
| dc.contributor.author | Lee, Jeonghyun | - |
| dc.contributor.author | Lim, Younghyun | - |
| dc.contributor.author | Choi, Jaehyouk | - |
| dc.date.accessioned | 2023-12-19T15:47:40Z | - |
| dc.date.available | 2023-12-19T15:47:40Z | - |
| dc.date.created | 2018-11-22 | - |
| dc.date.issued | 2018-06-20 | - |
| dc.description.abstract | This work presents an ultra-low-jitter hybrid injection-locked clock multiplier (ILCM) that cascades a ring ILCM and an LC ILCM to achieve a high multiplication factor of 114. A dual-purpose frequency calibrator (DPFC) that can calibrate the frequency drifts of the two VCOs, concurrently, consumes only 400 μW. The RMS-jitter of the output signal at 22.8 GHz was 153 fs. Due to the DPFC, RMS-jitter was maintained to be less than 180 fs, across supply voltages and temperatures. | - |
| dc.identifier.bibliographicCitation | IEEE Symposium on VLSI Circuits | - |
| dc.identifier.doi | 10.1109/VLSIC.2018.8502355 | - |
| dc.identifier.scopusid | 2-s2.0-85056858212 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/32727 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/8502355 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE | - |
| dc.title | 153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2018-06-18 | - |
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