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DC Field | Value | Language |
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dc.citation.endPage | 3477 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 3466 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 54 | - |
dc.contributor.author | Kim, Juyeop | - |
dc.contributor.author | Lim, Younghyun | - |
dc.contributor.author | Yoon, Heein | - |
dc.contributor.author | Lee, Yongsun | - |
dc.contributor.author | Park, Hangi | - |
dc.contributor.author | Cho, Yoonseo | - |
dc.contributor.author | Seong, Taeho | - |
dc.contributor.author | Choi, Jaehyouk | - |
dc.date.accessioned | 2023-12-21T18:16:37Z | - |
dc.date.available | 2023-12-21T18:16:37Z | - |
dc.date.created | 2019-10-11 | - |
dc.date.issued | 2019-12 | - |
dc.description.abstract | This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28-31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than -40 dBc. The active silicon area was 0.32 mm², and the total power consumption was 41.8 mW. | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.12, pp.3466 - 3477 | - |
dc.identifier.doi | 10.1109/JSSC.2019.2936765 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.scopusid | 2-s2.0-85072524537 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/29068 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8832221 | - |
dc.identifier.wosid | 000502721200020 | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Synthesizers | - |
dc.subject.keywordAuthor | Voltage-controlled oscillators | - |
dc.subject.keywordAuthor | Cascaded | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | Frequency synthesizers | - |
dc.subject.keywordAuthor | integrated phase noise (IPN) | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | millimeter-waveband (mmW-band) | - |
dc.subject.keywordAuthor | Phase locked loops | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | subsampling. | - |
dc.subject.keywordPlus | SUB-SAMPLING PLL | - |
dc.subject.keywordPlus | TUNING RANGE | - |
dc.subject.keywordPlus | PHASE-NOISE | - |
dc.subject.keywordPlus | LC-VCO | - |
dc.subject.keywordPlus | LOOP | - |
dc.subject.keywordPlus | OSCILLATOR | - |
dc.subject.keywordPlus | MULTIPLIER | - |
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