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김재준

Kim, Jae Joon
Circuits & Systems Design Lab.
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dc.citation.endPage 1253 -
dc.citation.number 15 -
dc.citation.startPage 1249 -
dc.citation.title IEICE ELECTRONICS EXPRESS -
dc.citation.volume 9 -
dc.contributor.author Byun, Sangjin -
dc.contributor.author Son, Chung Hwan -
dc.contributor.author Kim, Jae Joon -
dc.date.accessioned 2023-12-22T04:48:41Z -
dc.date.available 2023-12-22T04:48:41Z -
dc.date.created 2013-06-10 -
dc.date.issued 2012-08 -
dc.description.abstract A simple odd number frequency divider with 50% duty cycle is presented. The odd number frequency divider consists of a general odd number counter and the proposed duty cycle trimming circuit. The duty cycle trimming circuit can output 50% duty cycle with only additional six transistors. A prototype divide-by-5 circuit with 50% duty cycle was implemented for a 500-Mb/s similar to 5.6-Gb/s 1:10 CDR/DEMUX IC in a 0.13 mu m 1P8M CMOS process. -
dc.identifier.bibliographicCitation IEICE ELECTRONICS EXPRESS, v.9, no.15, pp.1249 - 1253 -
dc.identifier.doi 10.1587/elex.9.1249 -
dc.identifier.issn 1349-2543 -
dc.identifier.scopusid 2-s2.0-84865192349 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/2561 -
dc.identifier.url http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84865192349 -
dc.identifier.wosid 000307535900004 -
dc.language 영어 -
dc.publisher IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG -
dc.title Simple odd number frequency divider with 50% duty cycle -
dc.type Article -
dc.description.isOpenAccess TRUE -
dc.relation.journalWebOfScienceCategory Engineering, Electrical & Electronic -
dc.relation.journalResearchArea Engineering -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor odd number frequency divider -
dc.subject.keywordAuthor duty cycle -

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