A novel methodology for speeding up IC performance in 32nm FinFET
Cited 0 times inCited 1 times in
- A novel methodology for speeding up IC performance in 32nm FinFET
- Nguyen, Hung Viet; Ryu, Myunghwan; Kim, Youngmin
- Circuit designers; Double gate; FinFET; High performance; High-speed; IC designs; Low Power; Novel methodology; Signal propagation
- Issue Date
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- IEICE ELECTRONICS EXPRESS, v.9, no.4, pp.227 - 233
- This paper presents a novel methodology for IC speed-up in 32nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, we develop the boosting structures that can improve the signal propagation on interconnect significantly. Furthermore, the circuit area and power dissipation issues are also taken into account. With the addition of boosting path, the full booster can reduce the delay of interconnect as much as 50% while consuming merely more than 18% of power. In the high-speed and low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between the power consumption and high performance which play an important role in application-specific integration circuits in the 22nm node and beyond.
- ; Go to Link
Appears in Collections:
- ECE_Journal Papers
- Files in This Item:
can give you direct access to the published full text of this article. (UNISTARs only)
Show full item record
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.