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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)

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Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape

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Title
Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape
Author
Ryu, MyunghwanKim, Youngmin
Keywords
Effective length; Effective width; NRG; Post-lithography simulation; TCAD
Issue Date
2013
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v.10, no.11, pp.1 - 10
Abstract
In this paper, a simple and accurate modeling technique that analyzes a non-rectilinear gate (NRG) transistor with a simplified trapezoidal approximation method is proposed. To approximate a non-rectangular channel shape into a trapezoidal shape, we extract three geometry-dependent parameters from post-lithographic patterns: the minimum channel length from the slices (Lmin), maximum channel length from the slices (Lmax), and effective channel width (Weff). We slice the NRG transistor gate along its width, sort these slices according to their sizes, and then use trapezoidal approximation. A physics-based technology computer aided design (TCAD) simulation is used to verify our model in a typical 45-nm process. The developed model requires fewer computations and less runtime as compared to the previous approaches. Therefore, a full chip post-lithography analysis (PLA) becomes feasible.
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DOI
http://dx.doi.org/10.1587/elex.10.20130239
ISSN
1349-2543
Appears in Collections:
ECE_Journal Papers
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