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- Kim, Kyung Rok
- Nano-Electronic Emerging Devices Lab.
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Ternary full adder using multi-threshold voltage graphene barristors
- Author(s)
- Heo, Sunwoo, Kim, Sunmean, Kim, Kiyung, Lee, Hyeji, Kim, So-Young, Kim, Yun Ji, Kim, Seong Mo, Lee, Ho-In, Lee, Segi, Kim, Kyung Rok, Kang, Seokhyeong, Lee, Byoung Hun
- Issued Date
- 2018-10
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.39, no.12, pp.1948 - 1951
- Abstract
- Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable with the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- ISSN
- 0741-3106
- Keyword (Author)
- Graphene barristor, ternary full adder, multi threshold voltage ternary graphene barristor, ternary logic
- Keyword
- FIELD-EFFECT TRANSISTOR, DEVICE, DESIGN
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