File Download

There are no files associated with this item.

  • Find it @ UNIST can give you direct access to the published full text of this article. (UNISTARs only)
Related Researcher

이규호

Lee, Kyuho Jason
Intelligent Systems Lab.
Read More

Views & Downloads

Detailed Information

Cited time in webofscience Cited time in scopus
Metadata Downloads

A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses

Author(s)
Hong, InjoonBong, KyeongryeolShin, DongjooPark, SeongwookLee, Kyuho JasonKim, YouchangYoo, Hoi-Jun
Issued Date
2016-01
DOI
10.1109/JSSC.2015.2476786
URI
https://scholarworks.unist.ac.kr/handle/201301/24529
Fulltext
https://ieeexplore.ieee.org/document/7286768/
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.1, pp.45 - 55
Abstract
A low-power object recognition (OR) system with intuitive gaze user interface (UI) is proposed for battery-powered smart glasses. For low-power gaze UI, we propose a low-power single-chip gaze estimation sensor, called gaze image sensor (GIS). In GIS, a novel column-parallel pupil edge detection circuit (PEDC) with new pupil edge detection algorithm XY pupil detection (XY-PD) is proposed which results in 2.9x power reduction with 16x larger resolution compared to previous work. Also, a logarithmic SIMD processor is proposed for robust pupil center estimation, <1 pixel error, with low-power floating-point implementation. For OR, low-power multicore OR processor (ORP) is implemented. In ORP, task-level pipeline with keypoint-level scoring is proposed to reduce the number of cores as well as the operating frequency of keypoint-matching processor (KMP) for low-power consumption. Also, dual-mode convolutional neural network processor (CNNP) is designed for fast tile selection without external memory accesses. In addition, a pipelined descriptor generation processor (DGP) with LUT-based nonlinear operation is newly proposed for low-power OR. Lastly, dynamic voltage and frequency scaling (DVFS) for dynamic power reduction in ORP is applied. Combining both of the GIS and ORP fabricated in 65 nm CMOS logic process, only 75 mW average power consumption is achieved with real-time OR performance, which is 1.2x and 4.4x lower power than the previously published work.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
0018-9200
Keyword (Author)
Convolutional neural network (CNN)dynamic voltage and frequency scaling (DVFS)eye trackingfocal-plane processinggaze estimationlogarithmic approximationobject recognition (OR)smart glassesvision chip
Keyword
PROCESSOR

qrcode

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.