A 4b/cycle flash-assisted SAR ADC with comparator speed-boosting technique

Abstract

This paper presents flash-assisted successive approximation register (SAR) analog-to- digital converter (ADC) with an energy-efficient speed-boosting structure. The incorporation of a 3-bit flash sub-ADC into the SAR conversion path enables 4b/cycle conversion. For further speed boosting, the comparator is designed to include an auxiliary bootstrap capacitor which relieves settling-time bottleneck of capacitive digital-to-analog converters (C-DACs) in asynchronous SAR operation. This 4b/cycle conversion scheme requires only five switching events of C-DACs switching for 8-bit conversion, resulting in 22.32% reduction of additional switching energy. Prototype circuit implementation reveals that the proposed scheme achieves 75% speed enhancement compared to a conventional SAR scheme. For feasibility verification, the proposed flash-assisted SAR ADC was fabricated using a 0.18 mm CMOS process. Measured signal-to- noise and distortion (SNDR) and spurious-free dynamic range (SFDR) of the prototype were 48.49 dB and 64.95 dB respectively.