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Kim, Jae Joon
Circuits & Systems Design Lab.
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A 4b/cycle flash-assisted SAR ADC with comparator speed-boosting technique

Author(s)
Park, KyeonghwanPark, ChansamKim, Jae Joon
Issued Date
2018-04
DOI
10.5573/JSTS.2018.18.2.281
URI
https://scholarworks.unist.ac.kr/handle/201301/22843
Fulltext
http://www.jsts.org/html/journal/journal_files/2018/04/Year2018Volume18_02_20.pdf
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.2, pp.281 - 286
Abstract
This paper presents flash-assisted successive approximation register (SAR) analog-to- digital converter (ADC) with an energy-efficient speed-boosting structure. The incorporation of a 3-bit flash sub-ADC into the SAR conversion path enables 4b/cycle conversion. For further speed boosting, the comparator is designed to include an auxiliary bootstrap capacitor which relieves settling-time bottleneck of capacitive digital-to-analog converters (C-DACs) in asynchronous SAR operation. This 4b/cycle conversion scheme requires only five switching events of C-DACs switching for 8-bit
conversion, resulting in 22.32% reduction of additional switching energy. Prototype circuit implementation reveals that the proposed scheme achieves 75% speed enhancement compared to a conventional SAR scheme. For feasibility verification, the proposed flash-assisted SAR ADC was fabricated using a 0.18 mm CMOS process. Measured signal-to- noise and distortion (SNDR) and spurious-free dynamic range (SFDR) of the prototype were 48.49 dB and 64.95 dB respectively.
Publisher
IEEK PUBLICATION CENTER
ISSN
1598-1657
Keyword (Author)
Flash-assisted SAR ADC4b/cycle conversioncomparator speed-boosting techniqueswitching energyauxiliary bootstrap capacitor

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