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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 2001 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1993 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | - |
dc.citation.volume | 59 | - |
dc.contributor.author | Shringarpure, Ketan | - |
dc.contributor.author | Pan, Siming | - |
dc.contributor.author | Kim, Jingook | - |
dc.contributor.author | Fan, Jun | - |
dc.contributor.author | Achkir, Brice | - |
dc.contributor.author | Archambeault, Bruce | - |
dc.contributor.author | Drewniak, James L. | - |
dc.date.accessioned | 2023-12-21T21:37:00Z | - |
dc.date.available | 2023-12-21T21:37:00Z | - |
dc.date.created | 2017-09-08 | - |
dc.date.issued | 2017-12 | - |
dc.description.abstract | Power distribution network (PDN) design in high speed digital systems is a critical challenge for system performance. Common design methodologies refer to guidelines and engineering best practices while using simulations to evaluate the design. If the relation between the design choices and the performance parameters is known, the engineering is simpler. A lumped circuit model that relates physics and design geometry was proposed in an earlier study for modeling practical printed circuit board (PCB) PDN designs. In this paper, the lumped circuit model proposed earlier is used to develop a well-defined relation between the design geometry, the model elements, and the PDN impedance response features. The PDN impedance is simplified and broken down into common features for all PCB PDNs. These features are mapped to the model elements using sensitivity analysis and consequently to design geometry. The physics behind the relation between the response and geometry is reinforced with the current paths in different frequency ranges and generalized to common PDN designs on multilayer PCBs that use area fills for the power net. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.6, pp.1993 - 2001 | - |
dc.identifier.doi | 10.1109/TEMC.2017.2673851 | - |
dc.identifier.issn | 0018-9375 | - |
dc.identifier.scopusid | 2-s2.0-85028987270 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/22658 | - |
dc.identifier.url | http://ieeexplore.ieee.org/document/8000674 | - |
dc.identifier.wosid | 000408335300041 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Sensitivity Analysis of a Circuit Model for Power Distribution Network in a Multilayered Printed Circuit Board | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic; Telecommunications | - |
dc.relation.journalResearchArea | Engineering; Telecommunications | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Modeling PCB PDN | - |
dc.subject.keywordAuthor | power distribution network (PDN) | - |
dc.subject.keywordAuthor | power integrity | - |
dc.subject.keywordAuthor | printed circuit board (PCB) | - |
dc.subject.keywordPlus | SYSTEM-ON-PACKAGE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | EMI | - |
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