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Junctionless Sandwiched-gate Logic Design using Novel Device Structure File

Ryu, Myunghwan , Kim, Youngmin

Article Issue Date2018-08 View4
Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D IC File

Kim, Seung Won , Kang, Seokhyeong , Han, Ki Jin , Kim, Youngmin

Article Issue Date2016-07 View5
Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width File File

Ryu, Myunghwan , Bien, Franklin , Kim, Youngmin

Article Issue Date2016-01 View4
Optimization of analog circuits via simulation and a Lagrangian-type gradient-based method File

Lim, Eunji , Kim, Youngmin , Choi, Jaehyouk

Conference Paper Issue Date2015-12-09 View5
Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems File

Kim, Seungwon , Han, Ki Jin , Kim, Youngmin , Kang, Seokhyeong

Article Issue Date2019-07 View1
Sandwiched-Gate Inverter: Novel Device Structure for Future Logic Gates File

Ryu, Myunghwan , Bien, Franklin , Kim, Youngmin

Conference Paper Issue Date2015-09-09 View3
Theory and Practice of Lithium Ion Cell Design

Kim, Youngmin , Sung, Changhun , Baek, In Jun , Na, Hoyoung , Jeong, Kyeong-Min

Conference Paper Issue Date2018-11-30 View4
Unveiling the Role of Electrode-Level Heterogeneity Alleviated in Silicon–Graphite Electrode Under Operando Microscopy File File

Kim, Juyoung , Kim, Min-Ho , Kim, Youngmin , Kim, Myeong Seon , Choi, Ahreum , Jeong, Kyeong-Min , Lee, Hyun-Wook

Article Issue Date2023-03 View21
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