A New Design Methodology for Ternary Circuits and Systems

Abstract

Binary logic circuits have been the basis for modern computers to improve energy efficiency based on complementary metal-oxide-semiconductor (CMOS) technology. However, as the limitations of CMOS scaling are approaching, a new computing paradigm has been required. Multi-valued logic (MVL) circuits focus on minimizing hardware cost by processing more than two values per elementary operation. In recent years, various designs of three-valued (ternary) logic circuits have been proposed as the first step toward implementing MVL circuits with emerging technologies. The MVL is expected to improve the energy efficiency of digital circuits because fewer logic gates and interconnects are required than binary logic for the same function by calculating multiple values in a logic gate. In this paper, I propose an efficient design methodology for various ternary logic circuits using emerging technologies to demonstrate the potential of a ternary microprocessor. A logic synthesis methodology is proposed with a novel low-power circuit structure for ternary logic. Various arithmetic logic circuits for balanced and unbalanced ternary logic are designed, including ternary logic gates (STI, NMIN, NMAX), half adder, full adder, multiplier, latch, flip-flop (FF), static random-access memory (SRAM), binary to ternary (B2T) converter, ternary to binary converter (T2B), and ternary digital to analog converter (T-DAC). This study is expected to accelerate the implementation of ternary microprocessors using emerging technologies, and MVL is expected to attract attention as a new computing paradigm.