PVT-Robust Ultra-Low-Jitter Clock Multipliers Using an Injection-Locking Technique

Abstract

This thesis presents process-voltage-temperature (PVT)-robust ultra-low-jitter clock multipliers using an injection-locking technique. First, an injection-locked clock multiplier (ILCM) using a two-phase PVT-calibrator is proposed. The proposed PVT-calibration technique is based on the dual-loop architecture which consists of a main-voltage-controlled oscillator (VCO) and a replica-VCO. While the main-VCO is injection-locked and generates the precise target frequency, the real-time frequency variation of the replica-VCO can be monitored by the PVT-calibrator which adjusts the control voltage shared by the two identical VCOs. Using the two-phase calibration technique, the tradeoff between the calibration resolution and the lock time was removed. The proposed ILCM, fabricated in the 65-nm CMOS process, generated five different reference frequencies, i.e., 19.2, 28.8, 48.0, 57.6, and 96.0 MHz with a 19.2 MHz external clock. When injection-locked, the integrated jitter from 1 kHz to 10 MHz of the 96-MHz signal was 1.69 ps. The proposed PVT-calibrator restricted the phase noise degradation over the temperature range of 30 to 80 °C to less than 0.5 dB. Second, a fractional-resolution ILCM using a delay-locked-loop (DLL)-based PVT-calibrator is proposed. In this architecture, the ring-type VCO and the voltage-controlled delay line (VCDL) of the DLL consist of identical delay cells, and they share the same control voltage. Thus, by changing the ratio between the numbers of stages of the VCDL and the VCO, the frequency of the VCO can be calibrated at a target frequency, a non-integer times the reference frequency. The proposed ILCM, designed in the 65-nm CMOS process, generated output frequencies that range from 1.2 to 2.0 GHz with a frequency resolution of 40 MHz with a 400-MHz reference clock. When injection-locked, the integrated jitter from 1 kHz to 40 MHz of the 1.6-GHz signal was 440 fs. The proposed DLL-based PVT-calibrator restricted the degradations of phase noise and jitter over the temperature and the supply variations to less than 0.7 dB and 20%, respectively. Both architectures presented in this thesis can overcome real-time frequency drifts as well as static process variations; thus, excellent jitter performance can be sustained during any environmental variations.