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A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits File

Kim, Sunmean , Lee, Sung-Yun , Park, Sunghye , Kim, Kyung Rok , Kang, Seokhyeong

Article Issue Date2020-09 View7

A Metaheuristic Method for Fast Multi-Deck Legalization File

Do, SangGi

Thesis Issue Date2018-02 View12

A New Methodology for Reduced Cost of Resilience File

Kang, Seokhyeong , Kahng, Andrew B. , Li, Jiajia

Conference Paper Issue Date2014-05-22 View27

A novel design methodology for error-resilient circuits in near-Threshold computing File

Lee, Jaemin , Kim, Sunmean , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2016-10-26 View2

A Novel Methodology for Error-Resilient Circuits in Near-Threshold Computing File

Lee, Jaemin

Thesis Issue Date2017-08 View11

A Novel Ternary Multiplier based on Ternary CMOS Compact Model File

Kang, Yesung , Kim, Jaewoo , Kim, Sunmin , Shin, Sunhae , Jang, E-San , Jeong, Jae Won , Kim, Kyung Rok , Kang, Seokhyeong

Conference Paper Issue Date2017-05-22 View5

A preliminary analysis of domain coupling in package power distribution network File

Bae, Byoungjin , Kim, Seungwon , Kim, Youngmin , Kang, Seokhyeong , Kim, Il Joon , Kim, Kwangseok , Kang, Sunwon , Han, Ki Jin

Conference Paper Issue Date2017-08-30 View5

Accuracy-Configurable Adder for Approximate Arithmetic Designs File

Kahng, Andrew B. , Kang, Seokhyeong

Conference Paper Issue Date2012-06-05 View6

Active-Mode Leakage Reduction with Data-Retained Power Gating File

Kahng, Andrew B. , Kang, Seokhyeong , Park, Bongil

Conference Paper Issue Date2013-03-18 View5

An Improved Methodology for Resilient Design Implementation File

Kahng, Andrew B. , Kang, Seokhyeong , Li, Jiajia , De Gyvez, Jose Pineda

Article Issue Date2015-09 View7

An optimal gate design for the synthesis of ternary logic circuits File

Kim, Sunmean , Lim, Taeho , Kang, Seokhyeong

Conference Paper Issue Date2018-01-22 View4

An Optimal Gate Design for the Synthesis of Ternary Logic Circuits File

Kim, Sunmean

Thesis Issue Date2018-02 View9

An optimal operating point by using error monitoring circuits with an error-resilient technique File

Lee, Jaemin , Kim, Seungwon , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2015-10-05 View4

Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models File

Kim, Seungwon , Han, Ki Jin , Kang, Seokhyeong , Kim, Youngmin

Conference Paper Issue Date2014-11-05 View6

Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions File

Kang, Seokhyeong , Kahng, Andrew B.

Conference Paper Issue Date2012-03-25 View3

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic File

Kim, Sunmean , Lee, Sung-Yun , Park, Sunghye , Kang, Seokhyeong

Conference Paper Issue Date2019-05-21 View7

Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs

Kang, Seokhyeong , Kahng, AB , Kumar, R , Sartori, J

Conference Paper Issue Date2010-01-10 View5

Enhancing the Efficiency of Energy-Constrained DVFS Designs File

Kahng, Andrew B. , Kang, Seokhyeong , Kumar, Rakesh , Sartori, John

Article Issue Date2013-10 View5

Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study File

Kim, Seungwon , Han, Ki Jin , Kim, Youngmin , Kang, Seokhyeong

Conference Paper Issue Date2018-03-19 View5

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization File

Kim, Seungwon , Do, SangGi , Kang, Seokhyeong

Conference Paper Issue Date2017-06-20 View4

FPGA Controller Design for High Frequency LLC Resonant Converters File

Park, Hwa-Pyeong , Kang, Yesung , Kang, Seokhyeong , Jung, Jee-Hoon

Article Issue Date2020-09 View30

GRASP based metaheuristics for layout pattern classification File

Woo, Mingyu , Kim, Seungwon , Kang, Seokhyeong

Conference Paper Issue Date2017-11-13 View7

High-performance gate sizing with a signoff timer File

Kahng, Andrew B. , Kang, Seokhyeong , Lee, Hyein , Markov, Igor L. , Thapar, Pankit

Conference Paper Issue Date2013-11-20 View5

Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing Tools File

Kang, Seokhyeong , Kahng, Andrew B. , Lee, Hyein , Nath, Siddhartha , Wadhwani, Jyoti

Conference Paper Issue Date2013-06-02 View7

Many-Core Token-Based Adaptive Power Gating File

Kahng, Andrew B. , Kang, Seokhyeong , Rosing, Tajana Simunic , Strong, Richard

Article Issue Date2013-08 View4

MAPG: Memory Access Power Gating File

Jeong, Kwangok , Kahng, Andrew B. , Kang, Seokhyeong , Rosing, Tajana S. , Strong, Richard

Conference Paper Issue Date2012-03-12 View3

Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC File

Kim, Seungwon , Kang, Seokhyeong , Han, Ki Jin , Kim, Youngmin

Conference Paper Issue Date2015-03-04 View5

Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D IC File

Kim, Seung Won , Kang, Seokhyeong , Han, Ki Jin , Kim, Youngmin

Article Issue Date2016-07 View7

Novel approximate synthesis flow for energy-efficient FIR filter File

Kang, Yesung , Kim, Jaewoo , Kang, Seokhyeong

Conference Paper Issue Date2016-10-02 View5

Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology File

Kahng, Andrew B. , Kang, Seokhyeong , Kim, Seungwon , Samadi, Kambiz , Xu, Bangqi

Conference Paper Issue Date2019-03-25 View6

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems File

Kim, Seungwon , Han, Ki Jin , Kim, Youngmin , Kang, Seokhyeong

Article Issue Date2019-07 View3

Recovery-Driven Design: A Power Minimization Methodology for Error-Tolerant Processor Modules File

Kahng, Andrew B , Kang, Seokhyeong , Kumar, Rakesh , Sartori, John

Conference Paper Issue Date2010-06-15 View6

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors File

Kahng, Andrew B. , Kang, Seokhyeong , Kumar, Rakesh , Sartori, John

Article Issue Date2012-03 View5

Self-selective ferroelectric memory realized with semimetalic graphene channel File File

Jung, Sungchul , Park, Jinyoung , Kim, Junhyung , Song, Wonho , Jo, Jaehyeong , Park, Hyunjae , Kong, Myong , Kang, Seokhyeong , Sheeraz, Muhammad , Kim, Ill Won , et al

Article Issue Date2021-12 View22

Self-Selective Non-Destructive Read-Out for Ferroelectric Memory Based on Field Effect Transistor with Graphene Channel

Jung, Sungchul , Park, Jinyoung , Kim, Junhyung , Song, Wonho , Jo, Jaehyeong , Park, Hyunjae , Kong, Myong , Kang, Seokhyeong , Sheeraz, Muhammad , Kim, Ill Won , et al

Conference Paper Issue Date2022-07-18 View10

Sensitivity-Guided Metaheuristics for Accurate Discrete Gate Sizing

Hu, Jin , Kahnf, Andrew B. , Kang, Seokhyeong , Kim, Myung-Chul , Markov, Igor l

Conference Paper Issue Date2012-11-06 View4

Skew control methodology for useful-skew implementation File

Do, SANGgI , Kim, SEUNGWON , Kang, Seokhyeong

Conference Paper Issue Date2016-10-23 View8

Slack Redistribution for Graceful Degradation Under Voltage Overscaling File

Kahng, Andrew B. , Kang, Seokhyeong , Kumar, Rakesh , Sartori, John

Conference Paper Issue Date2010-01-18 View4

Smart Non-Default Routing for Clock Power Reduction File

Kahng, Andrew B. , Kang, Seokhyeong , Lee, Hyein

Conference Paper Issue Date2013-06-04 View5

Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits File

Chan, Wei-Ting J. , Kahng, Andrew B. , Kang, Seokhyeong , Kumar, Rakesh , Sartori, John

Conference Paper Issue Date2013-10-06 View6

Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimization File

Kim, Sangmin , Kang, Seokhyeong , Shin, Youngsoo

Article Issue Date2016-07 View6

TAP - Token-Based Adaptive Power Gating File

Kahng, Andrew B. , Kang, Seokhyeong , Rosing, Tajana , Strong, Richard

Conference Paper Issue Date2012-07-30 View5

Ternary full adder using multi-threshold voltage graphene barristors File File

Heo, Sunwoo , Kim, Sunmean , Kim, Kiyung , Lee, Hyeji , Kim, So-Young , Kim, Yun Ji , Kim, Seong Mo , Lee, Ho-In , Lee, Segi , Kim, Kyung Rok , et al

Article Issue Date2018-10 View19

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm File

Lee, Sung-Yun , Kim, Sunmean , Kang, Seokhyeong

Conference Paper Issue Date2019-05-21 View8

Toward Effective Utilization of Timing Exceptions in Design Optimization File

Kang, Seokhyeong , Jeong, Kwangok , Kahng, Andrew B.

Conference Paper Issue Date2010-03-23 View5

Wakeup scheduling and its buffered tree synthesis for power gating circuits File

Kim, Sangmin , Paik, Seungwhun , Kang, Seokhyeong , Shin, Youngsoo

Article Issue Date2016-03 View7

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